FPGA vs ASIC vs GPU — Circuit Copilot Glossary

Same math, three different silicon strategies. The choice comes down to flexibility, unit cost, and how many chips you need to make.

ASIC — Application-Specific Integrated Circuit

A chip built to do one thing. Custom silicon designed and taped out for a specific application: a Bitcoin miner, a network switch, Google's TPU, Apple's Neural Engine. Every transistor is placed intentionally for the target workload.

Pros: Highest possible performance-per-watt. Nothing wasted. Cheapest at scale (once the mask set is paid off).

Cons: Non-recurring engineering (NRE) costs of $10M-$100M+ to design and tape out. Can't be changed after fabrication. Only viable at volumes of ~10,000+ units.

GPU — Graphics Processing Unit

A general-purpose parallel processor. Originally built for graphics, now dominant for AI and scientific computing. Fixed hardware, but programmable via CUDA or ROCm.

Pros: Off-the-shelf, buy today. Software-programmable. Enormous ecosystem (PyTorch, TensorFlow, CUDA).

Cons: Not optimal for any specific task — you're paying for general-purpose flexibility. Power-hungry compared to an ASIC doing the same work. Cost-per-op is 5-20× worse than a purpose-built ASIC.

FPGA — Field-Programmable Gate Array

A chip full of configurable logic blocks that you wire together at boot time. The hardware itself is reprogrammed to match your circuit — not just the software.

Pros: Reconfigurable in the field. Good for low-volume custom logic, prototyping, protocols that change (5G basestations), or workloads that need deterministic timing (finance, defense).

Cons: 10-100× slower and 10-30× less power-efficient than an ASIC doing the same job. Harder to program than a GPU (Verilog/VHDL/HLS). Expensive per unit.

How to choose

Making 100 of something? FPGA or GPU. ASIC economics don't work.
Making 100 million of something? ASIC. Anything else is leaving money on the table.
Running neural nets, need it working next week? GPU.
Building a 5G basestation or a trading system? FPGA — protocols change, latency matters, volumes are moderate.
Google-scale AI inference? Custom ASIC (TPU) — they spend the NRE because they save it on power over billions of queries.

Modern hybrid: chiplet + FPGA fabric

New chips like Intel's Agilex or AMD's adaptive SoCs combine hard ASIC blocks (CPU cores, memory controllers) with FPGA fabric on the same package. Best of both worlds, at a premium price.