The number stopped being a real dimension around the 22nm node (2012). Everything since is a generational name. What you should actually look at is transistors per square millimeter.
Spoiler: nothing on a "3nm" chip is actually 3 nanometers. The number used to refer to the gate length of a transistor — the channel between source and drain. That stopped being literal around the 22nm node (~2012). Everything since is marketing.
A process node name today is a family identifier, not a measurement. When TSMC says "N3," they mean "this is our generation that comes after N5." The number is loosely correlated with transistor density but not equal to any physical feature.
The number you should actually care about is MTr/mm² — million transistors
per square millimeter. Rough density figures for recent TSMC nodes:
Doubling every two years used to be Moore's Law. We're now closer to ~1.5× every two years, and even that requires increasingly exotic process steps.
Below ~22nm, the physical gate length couldn't shrink as fast as the marketing names implied — quantum tunneling and short-channel effects blew up. Manufacturers kept making density gains through architectural tricks: FinFET (3D vertical fins instead of planar gates, ~2012), then gate-all-around (GAA) nanosheets (~2022 onwards).
Calling a node "5nm" or "3nm" was originally a way to claim density parity with the old scaling curve, not a real dimensional measurement.
TSMC N5, Samsung 5LPE, and Intel 7 are all called "5nm-ish" but have meaningfully different density, power, and performance. Intel renamed their entire roadmap in 2021 specifically because the old "Intel 10nm" was actually comparable to TSMC N7 — Intel's marketing had lagged the industry's marketing.
Today: Intel 4 ≈ TSMC N4 ≈ Samsung 4LPP, give or take. Intel 18A ≈ TSMC N2. These are rough alignments; the actual chips differ in important ways.